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? semiconductor components industries, llc, 2016 february, 2016 ? rev. p1 1 publication order number: ncp1370/d ncp1370 product preview dimmable quasi-resonant primary side current-mode controller for led tv backlight the ncp1370 is a pwm current mode controller targeting isolated flyback and non?isolated constant current topologies. the controller operates in a quasi?resonant mode to provide high efficiency. thanks to a novel control method, the device is able to precisely regulate a constant led current from the primary side. this removes the need for secondary side feedback circuitry, biasing and an opto?coupler. the device is highly integrated with a minimum number of external components. a robust suite of safety protection is built in to simplify the design. this device supports analog/digital dimming and both modes can be combined to enhance dimming precision. the ncp1370 has a programmable peak current limit to optimize design compatibility over a wide range of applications. the controller features a standby mode with reduced current consumption. features ? quasi?resonant peak current?mode control operation ? primary side sensing (no opto?coupler needed) ? wide v cc range ? source 300 ma / sink 500 ma totem pole driver with 12 v gate clamp ? precise led constant current regulation 1% typical ? line feed?forward for enhanced regulation accuracy ? low led current ripple ? 500 mv 1.2% guaranteed voltage reference for current regulation ? programmable cycle?by?cycle peak current limit ? low v cc(on) allowing to use a standby power supply to power the device ? analog or digital dimming ? wide temperature range of ?40 to + 125 c ? robust protection features ? led open circuit protection ? v cc over voltage protection ? secondary diode short protection ? output short circuit protection ? shorted current sense pin fault detection ? brown?out ? v cc under voltage lockout ? thermal shutdown ? pb?free, halide?free msl1 product typical applications ? tv backlight ? lighting with auxiliary power supply this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. ordering information 1 8 ncp1370x alyw 1 8 ncp1370 = specific device code x = device option (a or b) a = assembly location l = wafer lot y = year w = work week = pb?free package marking diagram soic?8 d suffix case 751 pin connections quasi?resonant pwm controller for led drivers (top view) dim vin vcc drv ilim zcd cs gnd 1
ncp1370 www. onsemi.com 2 1 2 3 45 8 6 7 v dim . . aux . v bias figure 1. typical application schematic for ncp1370 table 1. products table block or electrical parameter ncp1370b ncp1370a brown?out blanking time t bo(blank) 100 s 2 ms blanking circuit for leakage inductance reset detection on on v cc ovp auto?recovery latched switching cycles count before activating the output diode short circuit protection: v cs > v cs(stop) 4 cycles 4 cycles output diode short circuit protection auto?recovery latched adjustable ovp auto?recovery timer 1 second 4 seconds cs short circuit protection (impedance measurement before startup) on off high mains valley switching 3 rd (all hl valleys incremented by 1) 2 nd propagation delay from zcd to drv high state t zcd(dem) on on table 2. pin function description pin n pin name function pin description 1 ilim peak current limit and 2 nd over current protection this pin sets the cycle?by?cycle peak current limit threshold and the threshold for secondary diode short detection 2 zcd zero crossing detection connected to the auxiliary winding, this pin detects the core reset event. 3 cs current sense this pin monitors the primary peak current. 4 gnd ? the controller ground 5 drv driver output the driver?s output to an external mosfet 6 vcc supplies the controller this pin is connected to an external power supply. 7 vin brown?out input voltage sensing over voltage protection this pin observes the hv rail and protects the circuit in case of low main conditions. this pin also sense the line voltage for the valley selection and the line feed?forward a zener diode can also be used to pull?up the pin and stop the controller for adjustable ovp protection 8 dim analog / pwm dimming this pin is used for analog or pwm dimming control. an analog signal than can be varied between v dim(en) and v dim100 can be used to vary the current, or a pwm signal with an amplitude greater than v dim100 . this pin is also used for the off mode
ncp1370 www. onsemi.com 3 internal circuit architecture ilim zcd zero crossing detection valley selection cs ipkmax cs_stop qdrv vcc management vcc drv internal thermal shutdown management dim dimming type detection disable vin bo_nok cs_reset stop uvlo off stop cs_stop ipkmax bo_nok gnd stop qdrv aux. winding aux_scp aux_scp vcc_ovp line enable v vin ipkmax v ilimit v dd v ref v vin v ref v vly v dima disable cs_nok cs_nok control constant?current short circuit prot. clamp circuit v cc v ref v dima winding and output diode short circuit protection max. peak current limit cs short protection leading edge blanking feedforward peak current limits fault protection vcc over voltage v vin brown?out s r q v cs(stop) v ilimit v cs(stop) threshold generation over voltage protection ovp2 ovp2 off mode detection standby standby figure 2. internal circuit architecture
ncp1370 www. onsemi.com 4 table 3. maximum ratings table symbol rating value unit v cc(max) i cc(max) maximum power supply voltage, vcc pin, continuous voltage maximum current for vcc pin ?0.3, +35 internally limited v ma v drv(max) i drv(max) maximum driver pin voltage, drv pin, continuous voltage maximum current for drv pin ?0.3, v drv (note 1) ?500, +800 v ma v max i max maximum voltage on low power pins (except pins dim, drv and vcc) current range for low power pins (except pins drv and vcc) ?0.3, +5.5 ?2, +5 v ma v dim(max) maximum voltage for dim pin ?0.3, +7 v r j?a thermal resistance junction?to?air 289 c/w t j(max) maximum junction temperature 150 c operating temperature range ?40 to +125 c storage temperature range ?60 to +150 c esd capability, hbm model (note 2) 4 kv esd capability, mm model (note 2) 200 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. v drv is the drv clamp voltage v drv(high) when v cc is higher than v drv(high) . v drv is v cc unless otherwise noted. 2. this device series contains esd protection and exceeds the following tests: human body model 4000 v per mil?std?883, method 3 015. 3. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78 table 4. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v) for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v) description test condition symbol min typ max unit startup and supply circuits supply voltage startup threshold minimum operating voltage hysteresis v cc(on) ? v cc(off) internal logic reset equal to v cc(off) v cc increasing v cc decreasing v cc decreasing v cc(on) v cc(off) v cc(hys) v cc(reset) 11 9 1.8 9 12 9.5 ? 9.5 13 10 ? 10 v over voltage protection vcc ovp threshold v cc(ovp) 26 28 30 v v cc(off) noise filter v cc(reset) noise filter t vcc(off) t vcc(reset) ? ? 5 20 ? ? s startup current i cc(start) ? ? 100 a starting time from exiting off mode to 1 st drv pulse t cc(start) ? 250 s supply current device disabled/fault device enabled/no output load on pin 5 device switching (f sw = 65 khz) v cc > v cc(off) f sw = 65 khz c drv = 470 pf, f sw = 65 khz i cc1 i cc2 i cc3 0.8 ? ? 1.2 2.3 2.7 1.4 4.0 5.0 ma supply current in off mode i cc(off) 50 a current sense and ilim pin reference current for maximum peak current limit threshold i lim(ref) 190 200 210 a minimum value for internal v ilimit v pinilim < 0.5 v v ilimit(min) 0.5 v maximum value for internal v ilimit pin ilim open v ilimit(max) 2.34 2.6 2.86 v difference between internal v ilimit and ilim pin voltage v pinilim = 1.5 v v ilimit(offset) ?30 30 mv v cs(stop) at v pinilim = 1.5 v v pinilim = 1.5 v v cs(stop)1 2.037 2.1 2.163 v leading edge blanking duration for v ilim (t j = ?40 c to 125 c) t leb 280 330 380 ns minimum on?time (equal to t leb ) t on(min) 280 330 380 ns propagation delay from current detection to gate off?state t ilim ? 50 150 ns maximum on?time t on(max) 37.5 50 62.5 s 4. guaranteed by design
ncp1370 www. onsemi.com 5 table 4. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v) for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v) description unit max typ min symbol test condition current sense and ilim pin minimum threshold value for immediate fault protection acti- vation v pinilim < 0.5 v v cs(stop)min 0.7 v minimum threshold value for immediate fault protection acti- vation pin ilim open v cs(stop)max 3.64 v ratio between internal v cs(stop) and internal v ilimit k stop/ilimit 140 % leading edge blanking duration for v cs(stop) t bcs ? 200 ? ns current source for cs to gnd short detection i cs(short) 400 500 600 a timer for measuring cs to gnd short t cs(short) 12 17 22 s gate drive drive resistance drv sink drv source r snk r src ? ? 13 30 ? ? drive current capability drv sink (note 4) drv source (note 4) i snk i src ? ? 500 300 ? ? ma rise time (10 % to 90 %) c drv = 470 pf t r ? 40 ? ns fall time (90 % to 10 %) c drv = 470 pf t f ? 30 ? ns drv low voltage v cc = v cc(off) +0.2 v c drv = 470 pf, r drv =33 k v drv(low) 8 ? ? v drv high voltage v cc = 30 v c drv = 470 pf, r drv =33 k v drv(high) 10 12 14 v zero voltage detection circuit zcd threshold voltage v zcd increasing v zcd(thi) 30 50 70 mv zcd threshold voltage (note 4) v zcd decreasing v zcd(thd) 20 40 60 mv zcd hysteresis (note 4) v zcd increasing v zcd(hys) 8 ? ? mv threshold voltage for output short circuit or aux. winding short circuit detection v zcd(short) 0.8 1 1.2 v short circuit detection timer v zcd < v zcd(short) t ovld 70 90 110 ms auto?recovery timer duration t recovery 3 4 5 s input clamp voltage high state low state i pin1 = 3.0 ma i pin1 = ?2.0 ma v zcd(ch) v zcd(cl) ? ?0.9 8 ?0.6 ? ?0.3 v propagation delay from valley detection to drv high v zcd decreasing t zcd(dem) ? ? 480 ns delay from valley lockout output to drv latch set v zcd decreasing t leb4 125 250 375 ns blanking delay after on?time v ref > 100 mv t zcd(blank1) 1.2 1.6 2 s blanking delay after on?time at light load v ref < 75 mv t zcd(blank2) 0.6 0.8 1 s timeout after last demag transition t timo 5 6.5 8 s line feed?forward v vin to i cs(offset) conversion ratio k lff 15 17 19 a/v offset current maximum value v pinvin = 4.5 v i offset(max) 67.5 76.5 85.5 a constant current control reference voltage (after division by 2) (t j = 25 c) v ref 495 500 505 mv reference voltage (after division by 2) (t j = 0 c to 85 c) v ref 492 500 508 mv reference voltage (after division by 2) (t j =?40 c to 125 c) v ref 488 500 512 mv 4. guaranteed by design
ncp1370 www. onsemi.com 6 table 4. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v) for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v) description unit max typ min symbol test condition constant current control current sense lower threshold for detection of the leakage inductance reset time v cs(low) 25 55 85 mv blanking time for leakage inductance reset detection t cs(low) 130 ns v ref value below which the zcd blanking time is divided by 2 (light load) v ref decreases v ref(off) 75 mv v ref value above which zcd blanking time is t zcd(blank1) v ref increases v ref(on) 100 mv valley selection threshold for line range detection v in increasing (1 st to 2 nd valley or 1 st to 3 rd transition for v ref > 0.375 v) v vin increases v hl 2.28 2.4 2.52 v threshold for line range detection v in decreasing (2 nd to 1 st valley or 1 st to 3 rd transition for v ref > 0.375 v) v vin decreases v ll 2.18 2.3 2.42 v blanking time for line range detection t hl(blank) 15 25 35 ms valley thresholds (v ref = 500 mv) 1 st to 2 nd valley transition at ll and 2 nd to 3 rd valley hl (3 rd to 4 th valley hl for version b) v ref decreases 2 nd to 1 st valley transition at ll and 3 rd to 2 nd valley hl (4 th to 3 rd valley hl for version b), v ref incr. 2 nd to 4 th valley transition at ll and 3 rd to 5 th valley hl (4 th to 6 th valley hl for version b), v ref decr. 4 th to 2 nd valley transition at ll and 5 th to 3 rd valley hl (6 th to 4 th valley hl for version b), v ref incr. 4 th to 7 th valley transition at ll and 5 th to 8 th valley hl (6 th to 9 th valley hl for version b), v ref decr. 7 th to 4 th valley transition at ll and 8 th to 5 th valley hl (9 th to 6 th valley hl for version b), v ref incr. 7 th to 11 th valley transition at ll and 8 th to 12 th valley hl (9 th to 13 th valley hl for version b), v ref decr. 11 th to 7 th valley transition at ll and 12 th to 8 th valley hl (13 th to 9 th valley hl for version b), v ref incr. 11 th to 13 th valley transition at ll and 12 th to 15 th valley hl (13 th to 16 th valley hl for version b), v ref decr. 13 th to 11 th valley transition at ll and 15 th to 12 th valley hl (16 th to 13 th valley hl for version b), v ref incr. v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v vly1?2/2?3 v vly2?1/3?2 v vly2?4/3?5 v vly4?2/5?3 v vly4?7/5?8 v vly7?4/8?5 v vly7?11/8?12 v vly11?7/12?8 v vly11?13/12?15 v vly13?11/15?12 350 366 231 249 ? ? ? ? ? ? 373 390 248 267 150 165 75 100 30 40 396 414 265 285 ? ? ? ? ? ? mv valley thresholds in percentage of v ref 1 st to 2 nd valley transition at ll and 2 nd to 3 rd valley hl (3 rd to 4 th valley hl for version b) v ref decreases 2 nd to 1 st valley transition at ll and 3 rd to 2 nd valley hl (4 th to 3 rd valley hl for version b), v ref incr. 2 nd to 4 th valley transition at ll and 3 rd to 5 th valley hl (4 th to 6 th valley hl for version b), v ref decr. 4 th to 2 nd valley transition at ll and 5 th to 3 rd valley hl (6 th to 4 th valley hl for version b), v ref incr. 4 th to 7 th valley transition at ll and 5 th to 8 th valley hl (6 th to 9 th valley hl for version b), v ref decr. 7 th to 4 th valley transition at ll and 8 th to 5 th valley hl (9 th to 6 th valley hl for version b), v ref incr. 7 th to 11 th valley transition at ll and 8 th to 12 th valley hl (9 th to 13 th valley hl for version b), v ref decr. 11 th to 7 th valley transition at ll and 12 th to 8 th valley hl (13 th to 9 th valley hl for version b), v ref incr. 11 th to 13 th valley transition at ll and 12 th to 15 th valley hl (13 th to 16 th valley hl for version b), v ref decr. 13 th to 11 th valley transition at ll and 15 th to 12 th valley hl (16 th to 13 th valley hl for version b), v ref incr. v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v ref decreases v ref increases v vly1?2/2?3 v vly2?1/3?2 v vly2?4/3?5 v vly4?2/5?3 v vly4?7/5?8 v vly7?4/8?5 v vly7?11/8?12 v vly11?7/12?8 v vly11?13/12?15 v vly13?11/15?12 70 73 46 50 ? ? ? ? ? ? 74.5 78 49.5 53.5 30 33 15 20 6 8 79 83 53 57 ? ? ? ? ? ? % 4. guaranteed by design
ncp1370 www. onsemi.com 7 table 4. electrical characteristics (unless otherwise noted: for typical values t j = 25 c, v cc = 12 v) for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v) description unit max typ min symbol test condition dimming section dim pin voltage for zero output current (off voltage) v dim decreasing v dim(en) 0.67 0.7 0.73 v v dim(en) comparator hysteresis v dim increasing v en(hys) ? 50 ? mv dim pin voltage for maximum output current (t j = ?40 to 125 c) v dim100 2.9 3 3.1 v dim pin voltage for maximum output current at t j = 25 c v dim100 2.94 3 3.06 v dimming range v dim(range) ? 2.3 ? v clamping voltage for dim pin v dim(clp) ? 7 ? v dimming pin pull?up current source i dim(pullup) ? 5 ? a thermal shutdown thermal shutdown (note 4) device switching (f sw around 65 khz) t shdn 130 150 170 c thermal shutdown hysteresis (note 4) t shdn(hys) ? 50 ? c brown?out and ovp brown?out on level (ic start pulsing) v vin increasing v bo(on) 0.90 1 1.10 v brown?out off level (ic shuts down) v vin decreasing v bo(off) 0.85 0.9 0.95 v bo comparators delay t bo(delay) ? 30 ? s brown?out blanking time for version a t bo(blank1) 1.4 2 2.6 ms brown?out blanking time for version b t bo(blank2) 50 100 150 s brown?out pin bias current i bo(bias) ?250 ? 250 na clamped voltage (vin pin left open) vin pin open v vin(clamp) 3.9 4.1 4.3 v vin pin clamp series resistor r vin(clamp) 1 k vin pin detection level for ovp v vin increasing v ovp 4.75 5 5.25 v delay before ovp confirmation t ovp(delay) 50 s adjustable ovp auto?recovery timer (version b) t ovp(recovery1) 1 s adjustable ovp auto?recovery timer (version a) t ovp(recovery2) 4 s 4. guaranteed by design
ncp1370 www. onsemi.com 8 application information the ncp1370 is a led driver for flyback and non?isolated buck?boost / sepic converters. it implements a current?mode architecture quasi?resonant architecture to prevent valley?jumping instability. a proprietary circuitry ensures accurate regulation of the output current without the need of a secondary side feedback. the circuit features powerful protections to ensure a robust led driver design without the need of extra external components or overdesign. ? quasi?resonance curr ent?mode operation: implementing quasi?resonance operation in peak current?mode control, the ncp1370 optimizes the efficiency by switching in the valley of the mosfet drain?source voltage. thanks to smart control algorithm, the controller locks?out in a selected valley and remains locked until the input voltage or the output current set point significantly changes. ? primary side constant current control: thanks to a proprietary circuit, the controller accurately controls the output current without requiring a secondary side feedback (no optocoupler needed). an output current deviation below 2% is typically obtained. ? v cc over voltage protection: if the voltage on vcc pin exceeds an internal limit, the controller shuts down and waits 4 seconds before restarting pulsing (version b) or stays latched (a version). ? adjustable peak current limit: the cycle?by?cycle maximum peak current limit and the second over current protection level can be adjusted externally by connecting a resistor between ilim pin and ground. ? brown?out: the controller includes a brown?out circuit which safely stops the controller in case the input voltage is too low. the device will automatically restart if the line recovers. ? adjustable over voltage protection: by connecting a zener diode to the vin pin, an adjustable over voltage protection can be implemented to protect against open leds. upon detection, the controller waits 4 s (version a) or 1 s (version b) before attempting to restart switching. ? cycle?by?cycle peak curr ent limit: when the current sense voltage exceeds pin ilim voltage v ilim , the mosfet is turned off for the rest of the switching cycle. ? winding short?circuit protection (2 nd over current protection level): an additional comparator with a short leb filter (t bcs ) senses the cs signal and stops the controller if v cs reaches 140% of v ilimit ). for noise immunity reasons, this comparator is enabled only during the main leb duration t leb . ? output short?circuit protection: if a very low voltage is applied on zcd pin for 90 ms (nominal), the controllers assume that the output or the zcd pin is shorted to ground and enters shutdown. after waiting for 4 seconds, the controller restarts switching. ? linear or pwm dimming: the dim pin allows implementing both analog and pwm dimming. ? off mode: the ic enters in off mode after detecting a fault and whenever the dim pin voltage stays low during more than 4 seconds. in this mode, the ic is off and has a reduced current consumption. this allows simplifying the pcb design around the on/off opto?coupler. ? floating or short pin detection: the ncp1370 protections help passing safety tests. for instance, the circuit stops operating when the cs pin is grounded or when the gnd pin is open. constant current control capitalizing on the constant current control technique developed in the ncl3008x product, the ncp1370 accurately regulates the output current of a flyback converter from its primary side. by connecting the clamping capacitor of the flyback converter to the sense resistor as shown in the typical application schematic (figure 1), we have an image of the drain current waveform and of the leakage inductance current waveform. thus, by looking at the current sense pin waveform, the controller is able to detect the reset of the transformer leakage inductance. indeed, the leakage inductance limits the output rectifier peak current as shown in figure 3 where it is shown that: n sp * i d,pk < i l,pk . also, by monitoring the auxiliary winding voltage through the zcd pin, we can detect the end of conduction of the secondary rectifier.
ncp1370 www. onsemi.com 9 time t 1 t 2 t demag t on i l,pk n sp i d,pk i pri (t) i sec (t) time v aux (t) figure 3. flyback currents and auxiliary winding voltage in dcm the constant current control block picks up the leakage inductor current, the end of conduction of the output rectifier and controls the drain current to maintain the output current constant. we have: i out v ref 2n sp r sense (eq. 1) where: ? v ref is the output current internal reference ? n sp is the secondary to primary transformer turns ratio: n sp = n s / n p ? r sense is the current sense resistor the output current value is set by choosing the sense resistor: r sense v ref 2n sp i out (eq. 2) from (equation 1), the first key point is that the output current is independent of the inductor value. moreover, the leakage inductance does not influence the output current value as the reset time is taken into account by the controller. soft?start at startup or after recovering from a fault, there is a small internal soft?start of 200 s maximum. in addition, during startup, as the output voltage is zero volts, the demagnetization time is long and the constant current control block will slowly increase the peak current towards its nominal value as the output voltage grows. figure 5 shows a soft?start simulation example for a 9 w led power supply.
ncp1370 www. onsemi.com 10 figure 4. startup simulation showing the natural soft?start 0 4.00 8.00 12.0 16.0 1 0 200m 400m 600m 800m 2 604u 1.47m 2.34m 3.21m time in seconds 4.07m 0 200m 400m 600m 800m 3 4 i out v cs v out v control (a) (v) (v) adjustable cycle?by?cycle current limit the pin ilim allows adjusting the threshold for maximum peak current limit v ilimit and also the 2 nd over current protection (ocp2) threshold v cs(stop) which helps protecting against short circuit of the secondary winding or of the output diode. more precisely, the maximum peak current threshold v ilimit is equal to the ilim pin voltage and v cs(stop) value is derived from v ilimit . by connecting a resistor between ilim and gnd pins, the value of internal cycle?by?cycle current limit v ilimit is: v ilimit v ilim i lim(ref) r ilim (eq. 3) the threshold for immediate short circuit protection v cs(stop) is given by: v cs(stop) 1.4 v ilimit (eq. 4) practically, v ilimit can be adjusted from 0.5 v to 2.6 v, meaning v cs(stop) range is from 0.7 v to 3.64 v. when the current sense voltage exceeds the internal threshold v ilimit , the mosfet is turned off for the rest of the switching cycle. figure 5 shows the schematic of ilim pin.
ncp1370 www. onsemi.com 11 ilim i lim(ref) vdd ilim(min) ilim v r ilim ilim(max) v ilim v gain cs(stop) v v buffer clamp clamp figure 5. block diagram of ilim pin the cycle?by?cycle peak current limit threshold v ilimit also set the maximum duty cycle for a given application. the maximum duty cycle is given by: d max 1 v ref v ilimit t v t sw (eq. 5) where: ? t v is the valley duration ? t sw is the switching period for switching frequencies below 100 khz, the term t v /t sw can be neglected: d max 1 v ref v ilimit (eq. 6) winding and output diode short?circuit protection (ocp2) in parallel with the cycle?by?cycle sensing of the cs pin, another comparator with a reduced leb ( t bcs ) and a higher threshold (v cs(stop) ) is able to sense winding short?circuit and stop the controller. in version b, the controller stops the drv pulses after counting 4 cycles of v cs > v cs(stop) . the controller attempts to re?start after waiting 4 seconds. in version a, after counting 4 cycles of v cs > v cs(stop) , the controller stays latched. the controller is unlatched by one of the 3 following events: ? v cc < v cc(off) ? standby by v dim < v dim(en) during 4 seconds ? bo_nok becomes high after being unlatched, the controller goes into off mode. s r q q cs leb1 + ? s r q q vcc aux vcc management vdd vccreset drv ipkmax pwmreset v ilimit + ? leb2 v cs(stop) cs_stop vcontrol + ? stop from fault management block uvlo 4?s timer off 4?s timer 1 pulse 4 pulses or figure 6. winding short circuit protection, max. peak current limit circuits
ncp1370 www. onsemi.com 12 pwm or linear dimming detection the pin dim allows dimming the led light. analog dimming or digital (pwm) dimming can be used. if the power supply designer apply an analog signal varying from v dim(en) to v dim100 to the dim pin, the output current will increase or decrease proportionally to the voltage applied. for v dim = v dim100 , the power supply delivers the maximum output current. if a voltage lower than v dim(en) is applied to the dim pin, the drv pulses are disabled. thus, for digital dimming, a pwm signal with a low state value lower than v dim(en) and a high state value higher than v dim100 should be applied. the dim pin is pulled up internally by a small current source or resistor. thus, if the pin is left open, the controller is able to start. soft stop during pwm dimming the ncp1370 features an internal soft?stop of 200 s maximum in order to compensate the output current decrease caused by the soft?start during pwm dimming. practically, when v dim < v dim(en) , the controller decreases the peak current from its current state to nearly zero before stopping the drv pulses. this allows having a very good correlation between the dimming duty?cycle and the output current value when dimming at low duty?cycle. also, it is important to note that for good correlation between the dimming duty?cycle (which represent the expected output current value relative to the nominal value) and the actual measured output current, the high state duration of the dimming signal should not be below 200 s. figure 8 shows the drain source waveform during soft?stop. off mode with dim pin the off mode is entered when v dim stays below v dim(en) for 4 seconds. in this mode, ic consumption is reduced to i cc(off) (below 50 a). the off mode is exited only when v dim becomes higher than v dim(en) +v en(hys) . v dim100 v dim 0% i out 100% i out pwm dimming analog dimming v dim(en) 3v 0.7 v deep pwm dimming figure 7. pin dim chronograms v drain v dim figure 8. soft?stop
ncp1370 www. onsemi.com 13 v cc over voltage protection in order to protect itself against too high supply voltage, the controller features an over voltage protection for the v cc pin. when the v cc voltage reaches the v cc(ovp) threshold, the controller stops the drv pulses and shutdown. depending on the version, the controller goes in auto?recovery mode (version b) or in latched mode (version a). in the auto?recovery mode, the controller waits 4 s and tries to re?start. in order to restart pulsing, the controller goes through a complete sequence off mode fault mode (see fault management section for more information) in the latched mode, the controller stops pulsing and waits that one of the 3 following events occurs to reset the latch: ? v cc < v cc(off) ? standby by v dim < v dim(en) during 4 seconds ? bo_nok becomes high when the ovp latch is reset, the controller goes into off mode. v drv v cc v dim v cc(off) v dim(en) v cc(on) v cc(ovp) v dim(100) ?????? ?????? ?????? ?????? ?????? ?????? figure 9. v cc over voltage protection chronograms valley selection quasi?square wave resonant systems have a wide switching frequency excursion. the switching frequency increases when the output load decreases or when the input voltage increases. the switching frequency of such systems must be limited. the ncp1370 changes valley as the input voltage increases and as the output current set?point is varied during dimming. this limits the switching frequency excursion. once a valley is selected, the controller stays locked in the valley until the input voltage or the output current set?point varies significantly. the input voltage is sensed by the vin pin. the internal logic selects the operating valley according to vin pin voltage and dim pin voltage. by default, when the output current is not dimmed, the controller operates in the first valley at low line and in the second valley at high line for version a. for version b, the controller operates in the 3 rd valley at high line. table 5 summarizes the valley selected by the controller as a function of the output current and the input voltage. the numbers in blue are the selected valleys for version b.
ncp1370 www. onsemi.com 14 table 5. valley selection i out value at which the controller changes valley ( i out decreasing) vin pin voltage for valley change i out value at which the controller changes valley ( i out increasing) v vin decreases 0 ?? ll ?? 2.3 v ?? hl ?? 5 v i out decreases 100% 1 st 2 nd ( 3 rd ) 100% i out increases 75% 78% 2 nd 3 rd (4 th ) 50% 53% 4 th 5 th (6 th ) 30% 33% 7 th 8 th (9 th ) 15% 20% 11 th 12 th (13 th ) 6% 8% 13 th 15 th (16 th ) 0% 0% 0 ?? ll ?? 2.4 v ?? hl ?? 5 v v vin increases vin pin voltage for valley change zero crossing detection block the zcd pin allows detecting when the drain?source voltage of the power mosfet reaches a valley. a valley is detected when the voltage on pin 1 crosses down the 55?mv internal threshold. in order to decrease the capacitor value needed on zcd pin to turn?on the mosfet right in the valley or in some case remove it, a small delay (250 ns) is added internally before turning?on the mosfet. at startup or in case of extremely damped free oscillations, the zcd comparator may not be able to detect the valleys. to avoid such a situation, the ncp1370 features a time?out circuit that generates pulses if the voltage on zcd pin stays below the 55?mv threshold for 6.5 s. the time?out also acts as a substitute clock for the valley detection and simulates a missing valley in case of too damped free oscillations (figure 11). + ? zcd v zcd(th) time?out tblank clock + ? v zcd(short) tblank s r q q aux_scp 4?s timer enable_b 90?ms timer . figure 10. zcd block schematic
ncp1370 www. onsemi.com 15 figure 11. time?out chronograms low high clock timeout low high low high low high zcd comp 2 d n , 3 d r v zcd v () zcd th 4 3 14 12 15 16 17 the 3rd valley is validated the 3rd valley is not detected by the zcd comp timeout adds a pulse to account for the missing 3 rd valley the 2 d n valley is detected by the zcd comparator output short circuit protection because of the time?out function, if the zcd pin or the auxiliary winding is shorted, the controller will continue switching leading to improper regulation of the led current. moreover during an output short circuit, the controller will strive to maintain the constant current operation. in order to avoid these scenarios, a secondary timer starts counting when the zcd voltage is below the v zcd(short) threshold (figure 10). if this timer reaches 90 ms, the controller detects a fault and enters the auto?recovery fault mode: the controller stops pulsing and waits 4?s before going through a complete startup sequence. this protection is disabled when v dim < v dim(en) . line feed?forward because of the propagation delays, the mosfet is not turned?off immediately when the current set?point is reached. as a result, the primary peak current is higher than expected and the output current increases. to compensate the peak current increase brought by the propagation delays, a positive voltage proportional to the line voltage is added on the current sense signal. the amount of of fset voltage can be adjusted using the r cs resistor as shown in figure 12. v cs(offset) k lff v pinvin r cs (eq. 7) the offset voltage is applied only during the mosfet on?time. this offset voltage is always applied over the load range.
ncp1370 www. onsemi.com 16 bulk rail vin cs v dd r sense r cs i cs(offset) q_drv clamp rclamp vclamp + ? noise delay ovp v 4?s timer + ? bo_nok blanking time 1 v if bonok high 0.9 v if bonok low aux . s r q q ovp2 (1-s timer version b) figure 12. line feed?forward, adjustable ovp and brown?out schematic adjustable over voltage protection a clamping circuit on vin pin limits the voltage excursion to 4.1 v (figure 12). this level is high enough to allow good linearity of the line feedforward current for universal mains applications with an input voltage up to 265 v rms. when the zener diode starts conducting, it injects current inside the clamping circuit and the voltage on vin pin increases. when v vin exceeds v ovp during t ovp(delay) , the circuit detects an over voltage condition and stops the drv pulses. the controller waits until the ovp timer (t ovp(recovery) ) has elapsed (4 s for version a, 1 s for version b) and restarts switching. brown?out in order to protect the supply against a very low input voltage, the ncp1370 features a brown?out circuit with a fixed on/off threshold (figure 12). the controller is allowed to start if a voltage higher than 1 v is applied to the vin pin and shuts?down if the vin pin voltage decreases and stays below 0.9 v when the bo blanking timer has elapsed (bo_nok high). when a brown?out condition is detected, the circuit stops pulsing and goes into the off mode detailed in the ?fault management section?. pin connection faults ? cs pin short to ground the circuit senses the cs pin impedance every time it starts?up. if the measured impedance does not exceed 110 typically, the circuit does not start pulsing and shutdown. the circuit attempts to restart after waiting 4 seconds. in practice, it is recommended to place a minimum of 250 in series between the cs pin and the current sense resistor to take into account parasitic component effect and electrical parameters tolerance. ? fault of gnd pin connection if the gnd pin is properly connected, the current drawn from the positive terminal of the v cc capacitor flows out of the gnd pin to return to the negative terminal of the v cc capacitor. if the gnd pin is not connected, the circuit esd diodes offer another return path. the accidental non?connection of the gnd pin is monitored by detecting that one of the esd diode is conduction. practically, the esd diode of cs pin is monitored. if such a fault is detected for 200 s, the circuit stops generating drv pulses. fault management and startup sequence figure 13 and figure 14 shows the state diagrams of the ncp1370. off mode at startup, as long as v cc is not high enough, the controller is reset. its current consumption is i cc(start) . when v cc > v cc(on) , the controller goes in off mode and waits for the enable signal (v dim > v dim(en) ). in off mode, the ic consumption is very low (50 a maximum).
ncp1370 www. onsemi.com 17 the off mode is exited only if v cc > v cc(on) and v dim > v dim(en) . the controller then goes in fault mode. more generally, the off mode is entered upon the following events: ? v cc < v cc(off) ? brown?out edge ? v dim < v dim(en) after 4 seconds ? die over temperature (tsd) ? the 4?s auto?recovery timer has elapsed fault mode in this mode, the controller measures cs pin impedance. if cs pin is not shorted the controller is allowed to start the drv pulses. if cs pin is shorted, the controller starts the 4 seconds timer. no drv pulse is generated in this mode. ar mode in the auto?recovery mode, the 4 seconds timer is counting, drv is not pulsing. the 4 seconds timer starts counting when: ? v dim < v dim(en) ? a short circuit on cs pin is detected ? v cc > v cc(ovp) ? an output / auxiliary winding short circuit is detected: ?aux_scp high? ? second ocp level triggered when the 4?s timer has elapsed, the controller goes in off mode. adjustable ovp management when the adjustable ovp on vin pin is triggered, the controller stops the drv pulses and starts the ovp2 timer (4 s in version a, 1 s in version b). when the ovp2 timer has elapsed, the controller goes in fault mode and restart switching if no other fault is detected. latched protection (v cc ovp, output diode short circuit protection in version a) when v cc > v cc(ovp) or when the 2 nd ocp is triggered, the drv pulses stop and the controller is latched (figure 14). the latch resets when one of the 3 following events occurs: ? v cc < v cc(off) ? v dim < v dim(en) during 4 seconds ? bo_nok becomes high with states: reset controller is dead off controller is in off mode, i cc = i cc(off) (50 a max.) fault mode no switching, i cc = i cc1 run controller is switching ar mode the 4?s auto?recovery timer is counting, no switching ovp2 timer the ovp2 timer (4?s or 1?s) is counting, no drv pulses reset off cs_short high or vcc_ovp high or v dim < v dim(en) fault mode run ar mode ovp2 timer v dim > v dim(en) and v cc > v cc(on) timer ends (ar_end) or bo_nok edge or tsd_end or v cc < v cc(off) ovp2 bo_nok edge or tsd_end or v cc < v cc(off) v ddint por timer ends v cc too low cs_ok vcc_ovp high or v dim < v dim(en) or cs_stop or aux_scp ovp2 v dim > v dim(en) and all other faults low bo_nok edge or tsd_end or v cc < v cc(off) figure 13. fault state diagram with auto?recovery faults
ncp1370 www. onsemi.com 18 with states: reset controller is dead off controller is in off mode, i cc = i cc(off) (50 a max.) fault mode no switching, i cc = i cc1 run controller is switching ar mode the 4?s auto? recovery timer is counting, no switching ovp2 timer the ovp2 timer (4?s or 1? s) is counting, no drv pulses reset off cs_short high or v dim < v dim(en) fault mode run ar mode ovp2 timer v dim > v dim(en) and v cc > v cc(on) timer ends (ar_end) or bo_nok edge or tsd_end or v cc < v cc(off) ovp2 bo_nok edge or tsd_end or v cc < v cc(off) v ddint por timer ends v cc too low cs_ok v dim v dim(en) and all other faults low bo_nok edge or tsd_end or v cc < v cc(off) latch vcc_ovp high vcc_ovp high or cs_stop v cc < v cc(off) or bo_nok high or v dim < v dim(en) during 4 s figure 14. fault state diagram with latched faults ordering information device package type shipping ? NCP1370BDR2G soic?8 (pb free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1370 www. onsemi.com 19 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1370/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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